The present invention relates to a technique for manufacturing semiconductor devices, and in particular to a method for manufacturing semiconductor devices having DRAMs (Dynamic Random Access Memories).
DRAMs are semiconductor memories representing large storage capacity memories. The DRAMs tend to have increasingly larger memory capacities. From the view point of increasing the degree of integration of the memory cells of DRAMs, therefore, the area occupied by memory cells cannot help being reduced.
For the information storage capacitors in memory cells of DRAMs, however, it is known that a predetermined capacitance will be needed irrespective of the memory generation from the view point of the operation margin and software errors of the DRAMs and the scaling rule cannot be typically applied thereto.
Therefore, a capacitor structure allowing securement of a needed capacitance within a small limited occupied area is now being develpoped. As such a capacitor structure, a three-dimensional capacitor structure such as a so-called stacked capacitor having a capacitive insulating film between two poly-silicon layers is adopted.
In a typical structure of the stacked capacitors, a capacitor electrode is disposed over a selective MOSFET (Metal Oxide Semiconductor Field Effect Transistor). In this case, large capacitance can be secured by using a small occupied area. In addition, no diffusion layers are needed in the configuration of the capacitor. Therefore, the occurrence rate of software errors can be significantly reduced, and the needed capacitance can be advantageously reduced.
Various types are included in such stacked capacitor structures. Among them, a capacitor is disposed over a bit line in a so-called capacitor over bit line (hereafter abbreviated to COB) structure. In the COB structure, the underlying step of a storage electrode (storage node) is eliminated by the bit line. Therefore, the burden imposed on the process in forming the capacitor is advantageously reduced. Furthermore, since the bit line is shielded by the capacitor, a high signal-to-noise ratio value is advantageously obtained. By the way, a DRAM having a memory cell of a COB structure is described in JP-A-7-122654 published in May 12, 1995, for example.